(1) Field of the Invention
The present invention relates to a solid-state imaging device and a camera, and in particular to a MOS type solid-state imaging device such as a CMOS image sensor.
(2) Description of the Related Art
In recent years, various methods have been suggested for reading signals in a CMOS image sensor. Generally speaking, commonly used are CMOS image sensors of a column parallel output type in which a row of pixels is selected in a pixel array. Then, pixel signals generated in the selected pixels are read in parallel via a vertical signal line (also referred to as a column signal line). An image sensor that has also been suggested is of a column A/D type, which is provided with an A/D conversion circuit for each vertical signal line, so that a pixel signal is converted from analog to digital form inside the CMOS image sensor.
FIG. 15 is a schematic construction diagram of an image sensor shown in Japanese laid-open patent application No. 2005-323331 (hereinafter referred to as “Conventional technique 1”).
An image sensor 1 includes a pixel array 10, a drive control unit 7, a column processing unit 26, a reference signal generation unit 27, and an output circuit 28. The pixel array 10 is composed of a plurality of pixels 3 arranged in rows and columns. The drive control unit 7 is arranged on the periphery of the pixel array 10. The column processing unit 26 is composed of column A/D circuits arranged in correspondence with the columns of the pixel array 10. The reference signal generation unit 27 generates a reference signal RAMP whose level temporally changes with a predetermined rate of change.
The drive control unit 7 is composed of a horizontal scanning circuit (column scanning circuit) 12, a vertical scanning circuit (row scanning circuit) 14, and a timing control unit 40. The timing control unit 40 generates various kinds of internal clocks based on a master clock CLK0 input via a terminal 5a, and supplies the generated internal clocks for each circuit inside the image sensor 1.
Each of the pixels is connected to a row control line 15 derived from the vertical scanning circuit 14, and a vertical signal line 19 for transmitting a pixel signal to the column processing unit 26.
The column A/D circuit 25 includes a comparator 252, a counter 254, and a memory 256. The comparator 252 compares the level of the reference signal RAMP received from the reference signal generation unit 27 with the level of the pixel signal received from the pixel 3 via the vertical signal lines 19 (H0, H1, . . . ). The counter 254 counts input clock pulses. The memory 256 stores a digital value of the level of the pixel signal. The digital value is a difference between (i) a count value indicated by the counter 254 at a start of a predetermined period included in a horizontal period and (ii) a count value indicated by the counter 254 when the comparator 252 of a corresponding column shows coincidence between the level of the pixel signal and the level of the reference signal. This difference is referred to as “the number of counts counted by the counter” hereinafter. The pixel signal stored in the memory 256 is output outside by the horizontal scanning circuit 12 via the output circuit 28.
The following describes the operation of the image sensor shown in the conventional technique 1, particularly the operation when the pixel signal is A/D converted by the column A/D circuit 25.
FIG. 16 is a timing chart showing the operation of the image sensor according to the conventional technique 1.
The timing control unit 40 resets the counter 254 so that the count value of the counter 254 becomes its initial value “0”, and sets the counter 254 to a count-down mode. Also, the timing control unit 40 causes the pixel 3 in an arbitrary row Hx to read a pixel signal having a reset component ΔV. The pixel signals appear in the vertical signal lines 19 (H1, H2, . . . Hm) respectively. The timing control unit 40 supplies control data CN4 for the reference signal generation unit 27, when the pixel signals of the vertical signal lines 19 are stabilized (time t10). Upon receipt of the control data CN4, the reference signal generation unit 27 starts changing the level of the reference signal RAMP for the predetermined period included in the horizontal period. At the same time, the timing control unit 40 starts inputting a clock CK0 into the counter 254 (time t10) Upon receipt of the clock CK0, the counter 254 starts counting down from the initial value “0”.
The level of the reference signal RAMP changes for the predetermined period included in the horizontal period, and coincides with the reset component ΔV at a certain time (time t12). At this time, an output signal of the comparator 252 is inverted, which causes the counter 254 to stop counting down. A count value indicated by the counter 254 at this time is equivalent to the level of the reset component ΔV.
When a period for the count down elapses (time t14), the timing control unit 40 stops supplying the control data CN4 to the reference signal generation unit 27, and also stops inputting the clock CK0 into the counter 254.
Then, the timing control unit 40 sets the counter 254 to a count-up mode, and causes the pixel 3 in the row Hx to read a pixel signal having a signal component Vsig. A method for reading the pixel signal is the same as that for reading the reset component ΔV, except that the counter 254 is set to the count-up mode. As described above, the counter 254 is set to the count-down mode when the reset component ΔV is read, and set to the count-up mode when the signal component Vsig is read. In this way, a subtraction is automatically performed in the counter 254, thereby obtaining a count value equivalent to the level of the signal component Vsig.
The following describes an image sensor shown in the Japanese laid-open patent application No. 2006-33452 (hereinafter referred to as “Conventional technique 2”).
FIG. 17 is a schematic construction diagram of the image sensor shown in the conventional technique 2.
In the image sensor shown in the conventional technique 2, a clock CKdac that is supplied for the reference signal generation unit 27 is different from the clock CK0 that is input into the counter 254. ADAC 27a counts the clock CKdac, and reduces the voltage of the reference signal RAMP by ΔRAMP for each count. The amount of change per count ΔRAMP is set based on data indicating a slope of the reference signal RAMP (rate of a temporal change) included in the control data CN4.
FIG. 18 shows in detail the reference signal RAMP and the clock in the conventional technique 2.
The timing control unit 40 supplies the clock CK0 for the counter 254, and also selectively supplies, for the reference signal generation unit 27, a clock CKdac1 having the same frequency as the clock CK0, a clock CKdac2 having a frequency obtained by dividing the frequency of the clock CK0 by 2, and a clock CKdac4 obtained by dividing the frequency of the clock CK0 by 4. In this way, a reference signal RAMP1 is generated when the clock CKdac1 is supplied, a reference signal RAMP2 is generated when the clock CKdac2 is supplied, and a reference signal RAMP4 is generated when the clock CKdac4 is supplied. When the frequency of the clock CKdac is divided by 1/m (m is an integer), the slope of the reference signal RAMP is multiplied by 1/m, and the number of counts counted by the counter 254 is multiplied by m. This is equivalent to the gain being multiplied by m.
In the image sensor shown in the conventional technique 2, it is possible to change the gain when necessary, by appropriately changing the frequency of the clock CKdac that is input into the reference signal generation unit 27. However, the construction of the image sensor according to the conventional technique 2 is not fully satisfactory in terms of reducing the power consumption of the image sensor as a whole.
The reference signal generation unit 27 is driven by one of the clock CKdac1 having the same frequency as a reference frequency, the clock CKdac2 having a frequency of ½ of the reference frequency, and the clock CKdac4 having a frequency of ¼ of the reference frequency. On the other hand, the column A/D circuit 25 is driven by the clock CK0 having the same frequency as the reference frequency. Since the column A/D circuit 25 is driven by the clock CK0 that has the highest frequency among the internal clocks, the power consumption of the column A/D circuit 25 alone is relatively high. Furthermore, there are a large number of column A/D circuits 25, since the column A/D circuit 25 is provided in correspondence with each column of the pixel array 10. Consequently, the power consumption of the column A/D circuit 25 alone has a large impact on the power consumption of the image sensor as a whole.